1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device having a multilayer interconnection structure with aluminum (Al) interconnections in lower layers and copper (Cu) interconnections in upper layers.
2. Description of the Background Art
FIG. 26 is a cross-sectional view showing the structure of a conventional semiconductor device using aluminum interconnections. An element isolation insulating film 102 formed of a silicon oxide film (SiO2) is partially formed on a silicon (Si) substrate 101. Semiconductor elements such as MOSFETs 106 are formed in an element formation region defined by the element isolation insulating film 102. Each MOSFET 106 has a gate electrode 104 formed on an upper surface of the silicon substrate 101 with a gate insulating film 103 interposed therebetween, and a pair of source/drain regions 105 formed in the upper surface of the silicon substrate 101 with a channel formation region under the gate electrode 104 being interposed between the source/drain regions 105. While FIG. 26 shows gate electrodes 104 formed on the element isolation insulating film 102, the gate electrodes 104 of MOSFETs which are present in the depths of, or on this side of the paper extend on the element isolation insulating film 102.
An underlying insulating film 107 is formed all over the silicon substrate 101 to cover the MOSFETs 106 and the element isolation insulating film 102. The underlying insulating film 107 is formed of a silicon oxide film or a silicon oxide film implanted with an impurity element such as phosphorus (P) or boron (B). Contact holes 108 are formed in the underlying insulating film 107 and connected to the MOSFETs 106. First-layer interconnections 109, made of tungsten (W), are formed partially on the underlying insulating film 107. The first-layer interconnections 109, which are local interconnections, are short in length. The first-layer interconnections 109 are connected to the MOSFETs 106 through the tungsten which fills the contact holes 108.
A first interlayer insulating film 110 is formed on the underlying insulating film 107 to cover the first-layer interconnections 109. The first interlayer insulating film 110 is formed of a silicon oxide film or the like. Via holes 111 are formed in the first interlayer insulating film 110 and connected to the first-layer interconnections 109. The via holes 111 are filled with via plugs 112 made of tungsten or the like. Second-layer interconnections 113, made of an aluminum alloy such as Alxe2x80x94Cu, Alxe2x80x94Sixe2x80x94Cu, Alxe2x80x94Cuxe2x80x94Ti, etc., are partially formed on the first interlayer insulating film 110. The second-layer interconnections 113, which are short-distance interconnections, are relatively short in length. The second-layer interconnections 113 are connected to the first-layer interconnections 109 through the via plugs 112.
A second interlayer insulating film 114 is formed on the first interlayer insulating film 110 to cover the second-layer interconnections 113. The second interlayer insulating film 114 is formed of a silicon oxide film or the like. Via holes 115 are formed in the second interlayer insulating film 114 and connected to the second-layer interconnections 113. The via holes 115 are filled with via plugs 116 made of tungsten or the like. Third-layer interconnections 117, made of an aluminum alloy, are partially formed on the second interlayer insulating film 114. The third-layer interconnections 117, which are short-distance interconnections, are relatively short in length. The third-layer interconnections 117 are connected to the second-layer interconnections 113 through the via plugs 116.
A third interlayer insulating film 118 is formed on the second interlayer insulating film 114 to cover the third-layer interconnections 117. The third interlayer insulating film 118 is formed of a silicon oxide film or the like. Via holes 119 are formed in the third interlayer insulating film 118 and connected to the third-layer interconnections 117. The via holes 119 are filled with via plugs 120 made of tungsten or the like. Fourth-layer interconnections 121, made of an aluminum alloy, are partially formed on the third interlayer insulating film 118. The fourth-layer interconnections 121, which are long-distance interconnections or power-supply lines, are relatively long in length. Also, the fourth-layer interconnections 121 are thicker than the first- to third-layer interconnections 109, 113 and 117 in order to reduce the interconnection resistance and to increase the permissible current density. The fourth-layer interconnections 121 are connected to the third-layer interconnections 117 through the via plugs 120.
A fourth interlayer insulating film 122 is formed on the third interlayer insulating film 118 to cover the fourth-layer interconnections 121. The fourth interlayer insulating film 122 is formed of a silicon oxide film or the like. Via holes 123 are formed in the fourth interlayer insulating film 122 and connected to the fourth-layer interconnections 121. The via holes 123 are filled with via plugs 124 made of tungsten or the like. A fifth-layer interconnection 125 and a bonding pad 126, both made of an aluminum alloy, are formed partially on the fourth interlayer insulating film 122. The fifth-layer interconnection 125, which is a long-distance interconnection or a power-supply line, is relatively long in length. Also, the fifth-layer interconnection 125 is thicker than the first- to third-layer interconnections 109, 113 and 117 in order to reduce the interconnection resistance and to increase the permissible current density. The fifth-layer interconnection 125 and the bonding pad 126 are connected to the fourth-layer interconnections 121 through the via plugs 124.
A protective insulating film 127 is formed on the fourth interlayer insulating film 122 to cover the fifth-layer interconnection 125 and the bonding pad 126. The protective insulating film 127 is formed of a silicon oxide film, a silicon nitride film (Si3N4), a silicon oxynitride film (SiON), or a composite film thereof. A buffer coat film 128 is formed on the protective insulating film 127 when required. The buffer coat film 128 is made of polyimide or the like.
An opening 129, having its bottom defined by the bonding pad 126, is formed in part of the protective insulating film 127 and the buffer coat film 128. A bonding wire 130 is inserted in the opening 129 and bonded to the bonding pad 126. The bonding wire 130 is made of gold (Au), aluminum, or the like. A metal layer 131 is formed at the interface between the bonding wire 130 and the bonding pad 126. When the bonding wire 130 and the bonding pad 126 are made of different materials, the metal layer 131 is a layer of a compound of the material metal of the bonding wire 130 and that of the bonding pad 126. When the two are made of the same material, the metal layer 131 is an inter-diffusion layer of the material metals.
The buffer coat film 128 and the bonding wire 130 are sealed with a molding resin 132.
FIGS. 27 to 35 are cross-sectional views showing a sequence of process steps for manufacturing the semiconductor device shown in FIG. 26. First, referring to FIG. 27, the element isolation insulating film 102 is formed in the element isolation region of the silicon substrate 101 by a LOCOS (Local Oxidation of Silicon) isolation or trench isolation process. Next, the MOSFETs 106 are formed in the element formation region of the silicon substrate 101 by known processes such as CVD (Chemical Vapor Deposition), anisotropic dry etching, ion implantation, etc. Next, the underlying insulating film 107 is formed by CVD over the entire surface.
Next, referring to FIG. 28, the contact holes 108 are formed in the underlying insulating film 107 by photolithography and anisotropic dry etching. Next, a barrier metal 109a, composed of a stacked film of a titanium (Ti) film and a titanium nitride (TiN) film, is formed over the entire surface by PVD (Physical Vapor Deposition). The formation of the barrier metal 109a offers good ohmic contact with the silicon. Next, a tungsten film 109b is formed all over the surface by thermal CVD using reduction of tungsten hexafluoride (WF6) and hydrogen (H2). Setting the temperature at about 375 to 450xc2x0 C. during the film formation provides the tungsten film 109b with good step coverage. As a result the contact holes 108 can be easily filled with the tungsten film 109b even when they have a high aspect ratio. Also, the titanium nitride film used as the barrier metal 109a has the effect of preventing the silicon substrate 101 from being damaged by tungsten hexafluoride during the formation of the tungsten film 109b. 
Next, the barrier metal 109a and the tungsten film 109b are patterned by photolithography and anisotropic dry etching to form the first-layer interconnections 109. While the tungsten interconnections have interconnection resistance about three times higher than that of the aluminum interconnections, they can be formed by a simpler formation process since they do not need formation of contact plugs. The tungsten interconnections are hence generally used as short interconnections (local interconnections etc.).
Next, the first interlayer insulating film 110 is formed all over the surface to cover the first-layer interconnections 109. The first interlayer insulating film 110, which underlies the second-layer interconnections 113, requires a sufficient degree of flatness. Accordingly, the first interlayer insulating film 110 is formed through a process of forming all over the surface a silicon oxide film thicker than the target thickness of the first interlayer insulating film 110 by CVD using high-density plasma etc. and a surface planarization process of polishing the surface of the silicon oxide film for a given thickness by chemical mechanical polishing (CMP) using a potassium-hydroxide (KOH)-or ammonia-water (NH4OH)-based silica abrasive. Alternatively, the first interlayer insulating film 110 is formed through a process of forming all over the surface a silicon oxide film thinner than the target thickness of the first interlayer insulating film 110 by CVD and a process of forming an SOG (Spin On Glass) film on the silicon oxide film by spin coating.
Next, referring to FIG. 29, the via holes 111 are formed in the first interlayer insulating film 110 by photolithography and anisotropic dry etching. Next, a foundation film 112a, a stacked film of a titanium film and a titanium nitride film, is formed all over the surface by PVD or CVD. The formation of the foundation film 112a offers good contact with the first-layer interconnections 109. Next, a tungsten film 112b with good step coverage is formed all over the surface by a process similar to that used to form the tungsten film 109b. Next, the tungsten film 112b and the foundation film 112a are polished until the top surface of the first interlayer insulating film 110 is exposed, by CMP using a hydrogen-peroxide (H2O2)-based alumina abrasive or silica abrasive. The foundation film 112a and the tungsten film 112b in the via holes 111 thus remain unpolished as the via plugs 112.
Next, referring to FIG. 30, a foundation film 113a, e.g. formed of a titanium film, a titanium nitride film, or a stacked film thereof, is formed all over the surface by PVD. Next, an aluminum alloy film 113b, e.g. made of Alxe2x80x94Cu, Alxe2x80x94Sixe2x80x94Cu, Alxe2x80x94Cuxe2x80x94Ti, is formed all over the surface by PVD. Next, an antireflection film 113c, made of titanium nitride, is formed all over the surface by PVD. Next, these films 113a to 113c are patterned by photolithography and anisotropic dry etching to form the second-layer interconnections 113. Next, the second interlayer insulating film 114 with good surface flatness is formed all over the surface by a process similar to that used to form the first interlayer insulating film 110.
Next, referring to FIG. 31, by process steps similar to those shown in FIGS. 29 and 30, (a) the via holes 115 are formed in the second interlayer insulating film 114, (b) a foundation film 116a and a tungsten film 116b are formed all over the surface, (c) these films 116a and 116b are polished to form the via plugs 116, (d) a foundation film 117a, an aluminum alloy film 117b, and an antireflection film 117c are formed all over the surface, (e) these films 117a to 117c are patterned to form the third-layer interconnections 117, and (f) the third interlayer insulating film 118 is formed all over the surface.
Next, referring to FIG. 32, by process steps similar to those shown in FIGS. 29 and 30, (a) the via holes 119 are formed in the third interlayer insulating film 118, (b) a foundation film 120a and a tungsten film 120b are formed all over the surface, (c) these films 120a and 120b are polished to form, the via plugs 120, (d) a foundation film 121a, an aluminum alloy film 121b, and an antireflection film 121c are formed all over the surface, (e) these films 121a to 121c are patterned to form the fourth-layer interconnections 121, and (f) the fourth interlayer insulating film 122 is formed all over the surface.
Next, referring to FIG. 33, by process steps similar to those shown in FIGS. 29 and 30, (a) the via holes 123 are formed in the fourth interlayer insulating film 122, (b) a foundation film 124a and a tungsten film 124b are formed all over the surface, (c) these films 124a and 124b are polished to form the via plugs 124, (d) a foundation film 125a, an aluminum alloy film 125b, and an antireflection film 125c are formed all over the surface, and (e) these films 125a to 125c are patterned to form the fifth-layer interconnection 125. The bonding pad 126, composed of a foundation film 126a, an aluminum alloy film 126b, and an antireflection film 126c, is also formed during the patterning of the films 125a to 125c. 
Next, referring to FIG. 34, the protective insulating film 127 is formed by CVD all over the surface. Next, the buffer coat film 128 is formed by CVD all over the surface. Next, the buffer coat film 128 and the protective insulating film 127 are partially removed by photolithography and anisotropic dry etching to form the opening 129. At this time, the antireflection film 126c of the bonding pad 126 is also removed to expose the top surface of the aluminum alloy film 126b. Next, the semiconductor wafer is separated by dicing into individual chips and the chips are bonded on the back to leadframes or mount boards (neither is shown) with resin or solder.
Next, referring to FIG. 35, the bonding wire 130 is inserted in the opening 129 and bonded to the aluminum alloy film 126b of the bonding pad 126 by an ultrasonic or thermocompression process. At this time the metal layer 131 is formed at the interface between the bonding wire 130 and the bonding pad 126.
Finally, the entirety shown in FIG. 35 is sealed with the molding resin 132 to obtain the structure shown in FIG. 26.
Recently, for the purpose of realizing high speed operation and high performance of devices, interconnections chiefly made of copper (copper interconnections) are used in place of conventional interconnections chiefly made of aluminum (aluminum interconnections), so as to reduce the interconnection resistance and increase the permissible current density; the copper interconnections have lower resistance and higher reliability than the aluminum interconnections.
FIG. 36 is a cross-sectional view showing the structure of a conventional semiconductor device using copper interconnections. An element isolation insulating film 102 is formed in the element isolation region of the silicon substrate 101 and MOSFETs 106 are formed in the element formation region.
An underlying insulating film 151 is formed on the entire surface of the silicon substrate 101 to cover the MOSFETs 106 and the element isolation insulating film 102. In the underlying insulating film 151, contact holes 152 are formed and connected to the MOSFETs 106 and interconnection trenches 153 are formed and connected to the contact holes 152. First-layer interconnections 154, made of tungsten, are formed to fill the interconnection trenches 153. The first-layer interconnections 154, which are local interconnections, are short in length. The first-layer interconnections 154 are connected to the MOSFETs 106 through the tungsten which fills the contact holes 152.
A first interlayer insulating film 155 is formed on the underlying insulating film 151. In the first interlayer insulating film 155, via holes 156 are formed and connected to the first-layer interconnections 154 and interconnection trenches 157 are formed and connected to the via holes 156. Second-layer interconnections 158, made of copper, are formed to fill the interconnection trenches 157. The second-layer interconnections 158, which are short-distance interconnections, are relatively short in length. The second-layer interconnections 158 are connected to the first-layer interconnections 154 through the copper which fills the via holes 156.
A second interlayer insulating film 159 is formed on the first interlayer insulating film 155. In the second interlayer insulating film 159, via holes 160 are formed and connected to the second-layer interconnections 158 and interconnection trenches 161 are formed and connected to the via holes 160. Third-layer interconnections 162, made of copper, are formed to fill the interconnection trenches 161. The third-layer interconnections 162, which are short-distance interconnections, are relatively short in length. The third-layer interconnections 162 are connected to the second-layer interconnections 158 through the copper in the via holes 160.
A third interlayer insulating film 163 is formed on the second interlayer insulating film 159. In the third interlayer insulating film 163, via holes 164 are formed and connected to the third-layer interconnections 162 and interconnection trenches 165 are formed and connected to the via holes 164. Fourth-layer interconnections 166, made of copper, are formed to fill the interconnection trenches 165. The fourth-layer interconnections 166, which are long-distance interconnections or power-supply lines, are relatively long in length. Also, the fourth-layer interconnections 166 are thicker than the first- to third-layer interconnections 154, 158 and 162 in order to reduce the interconnection resistance and increase the permissible current density. The fourth-layer interconnections 166 are connected to the third-layer interconnections 162 through the copper in the via holes 164.
A fourth interlayer insulating film 167 is formed on the third interlayer insulating film 163. In the fourth interlayer insulating film 167, via holes 168 are formed and connected to the fourth-layer interconnections 166 and an interconnection trench 169L and an electrode trench 169P are formed and connected to the via holes 168. A fifth-layer interconnection 170, made of copper, is formed to fill the interconnection trench 169L. The fifth-layer interconnection 170, which is a long-distance interconnection or a power-supply line, is relatively long in length. Also, the fifth-layer interconnection 170 is thicker than the first- to third-layer interconnections 154, 158 and 162 in order to reduce the interconnection resistance and increase the permissible current density. Further, a bonding pad 171, made of copper, is formed to fill the electrode trench 169P. The fifth-layer interconnection 170 and the bonding pad 171 are connected to the fourth-layer interconnections 166 through the copper in the via holes 168.
A protective insulating film 172 is formed on the fourth interlayer insulating film 167. The protective insulating film 172 is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a composite film thereof. A buffer coat film 173 is formed on the protective insulating film 172 when required. The buffer coat film 173 is made of polyimide, for example.
An opening 174, having its bottom defined by the bonding pad 171, is formed in part of the protective insulating film 172 and the buffer coat film 173. A bonding wire 175 is inserted in the opening 174 and bonded to the bonding pad 171. The bonding wire 175 is made of gold, aluminum, or the like. A metal layer 176 is formed at the interface between the bonding wire 175 and the bonding pad 171. When the bonding wire 175 and the bonding pad 171 are made of different materials, the metal layer 176 is a layer of a compound of the material metal of the bonding wire 175 and that of the bonding pad 171. When the two are made of the same material, the metal layer 176 is an inter-diffusion layer of the material metals.
The buffer coat film 173 and the bonding wire 175 are sealed with a molding resin 177.
FIGS. 37 to 48 are cross-sectional views showing a sequence of process steps for manufacturing the semiconductor device shown in FIG. 36. First, referring to FIG. 37, the element isolation insulating film 102 and the MOSFETs 106 are formed by a process similar to that shown in FIG. 27. Next, a silicon oxide film 151a (which may be implanted with an impurity element such as phosphorus or boron), a silicon nitride film 151b, and a silicon oxide film 151c are deposited in this order all over the surface by thermal CVD or plasma CVD, so as to form the underlying insulating film 151.
Next, referring to FIG. 38, the interconnection trenches 153 are formed in the silicon oxide film 151c by photolithography and anisotropic dry etching. The anisotropic dry etching is carried out under such conditions that silicon oxide film is easily etched and silicon nitride film is not easily etched so that the silicon nitride film 151b can function as an etching stopper. Next, the contact holes 152 are formed in the underlying insulating film 151 by photolithography and anisotropic dry etching.
Next, referring to FIG. 39, a barrier metal 154a, formed of a stacked film of a titanium film and a titanium nitride film, is formed over the entire surface by PVD or CVD. The formation of the barrier metal 154a offers good ohmic contact with silicon. Next, a tungsten film 154b is formed all over the surface by thermal CVD using reduction of tungsten hexafluoride and hydrogen.
Next, referring to FIG. 40, the tungsten film 154b and the barrier metal 154a are polished by CMP using a hydrogen-peroxide-based alumina abrasive until the top surface of the underlying insulating film 151 is exposed. The barrier metal 154a and the tungsten film 154b in the interconnection trenches 153 and the contact holes 152 thus remain unpolished as the first-layer interconnections 154.
Next, referring to FIG. 41, by process steps similar to those shown in FIGS. 37 and 38, (a) a silicon oxide film 155a, a silicon nitride film 155b, and a silicon oxide film 155c are deposited in this order all over the surface to form the first interlayer insulating film 155, (b) the interconnection trenches 157 are formed in the silicon oxide film 155c by using the silicon nitride film 155b as an etching stopper, and (c) the via holes 156 are formed in the first interlayer insulating film 155.
Next, referring to FIG. 42, a foundation film 158a is formed all over the surface by PVD or CVD; for example, the foundation film 158a is formed of a tantalum (Ta) film, a tantalum nitride (TaN) film, a stacked film of a tantalum film and a tantalum nitride film, a titanium nitride film, or a stacked film of a titanium film and a titanium nitride film. The formation of the foundation film 158a prevents copper contained in the copper interconnections from diffusing into the nearby insulating films (silicon oxide film etc.). Next, a copper seed film (not shown) as a foundation film for electroplating is formed all over the surface by PVD or CVD. Next, a copper film 158b is formed all over the surface by electroplating using a plating solution mainly containing copper sulfate.
Next, referring to FIG. 43, the copper film 158b and the foundation film 158a are polished by CMP using a hydrogen-peroxide-based alumina abrasive until the top surface of the first interlayer insulating film 155 is exposed. The foundation film 158a and the copper film 158b in the interconnection trenches 157 and the via holes 156 thus remain unpolished as the second-layer interconnections 158.
The sequence of process steps for forming the interconnections, i.e. previously forming the via holes and interconnection trenches in the interlayer insulating film, forming a metal film thick enough to entirely fill the via holes and interconnection trenches, and then removing the unwanted part of the metal film by CMP, is known as a dual damascene process.
Next, referring to FIG. 44, a silicon nitride film 159a which functions as a copper diffusion preventing film, a silicon oxide film 159b, a silicon nitride film 159c, and a silicon oxide film 159d are deposited in this order on the entire surface by, e.g. plasma CVD, so as to form the four-layered second interlayer insulating film 159. Next, by process steps similar to those shown in FIGS. 41 to 43, (a) the interconnection trenches 161 are formed in the silicon oxide film 159d using the silicon nitride film 159c as an etching stopper, (b) the via holes 160 are formed in the second interlayer insulating film 159, (c) a foundation film 162a and a copper seed film (not shown) are formed all over the surface, (d) a copper film 162b is formed all over the surface, and (e) the copper film 162b and the foundation film 162a are polished until the top surface of the second interlayer insulating film 159 is exposed, so as to form the third-layer interconnections 162.
Next, referring to FIG. 45, by a process similar to that shown in FIG. 44, (a) a silicon nitride film 163a, a silicon oxide film 163b, a silicon nitride film 163c, and a silicon oxide film 163d are deposited in this order all over the surface to form the four-layered third interlayer insulating film 163, (b) the interconnection trenches 165 are formed in the silicon oxide film 163d by using the silicon nitride film 163c as an etching stopper, (c) the via holes 164 are formed in the third interlayer insulating film 163, (d) a foundation film 166a and a copper seed film (not shown) are formed all over the surface, (e) a copper film 166b is formed all over the surface, and (f) the copper film 166b and the foundation film 166a are polished until the top surface of the third interlayer insulating film 163 is exposed, so as to form the fourth-layer interconnections 166.
Next, referring to FIG. 46, by a process similar to that shown in FIG. 44, (a) a silicon nitride film 167a, a silicon oxide film 167b, a silicon nitride film 167c, and a silicon oxide film 167d are deposited in this order all over the surface to form the four-layered fourth interlayer insulating film 167, (b) the interconnection trench 169L and the electrode trench 169P are formed in the silicon oxide film 167d using the silicon nitride film 167c as an etching stopper, (c) the via holes 168 are formed in the fourth interlayer insulating film 167, (d) a foundation film 170a and a copper seed film (not shown) are formed all over the surface, (e) a copper film 170b is formed all over the surface, and (f) the copper film 170b and the foundation film 170a are polished until the top surface of the fourth interlayer insulating film 167 is exposed, so as to form the fifth-layer interconnection 170. The bonding pad 171 composed of a foundation film 171a and a copper film 171b is also formed in the electrode trench 169P during the process of polishing the copper film 170b and the foundation film 170a. 
Next, referring to FIG. 47, a fine silicon nitride film 172a, which functions as a copper diffusion preventing film, and an insulating film 172b, e.g. a silicon oxide film, are formed by CVD in this order all over the surface, so as to form the protective insulating film 172. Next, the buffer coat film 173 is formed by CVD all over the surface. Next, the buffer coat film 173 and the protective insulating film 172 are partially removed by photolithography and anisotropic dry etching to form the opening 174. This exposes part of the top surface of the bonding pad 171. Next, the semiconductor wafer is separated by dicing into individual chips and the chips are bonded on the back to leadframes or mount boards (neither is shown) with resin or solder.
Next, referring to FIG. 48, the bonding wire 175 is inserted in the opening 174 and bonded to the bonding pad 171 by an ultrasonic or thermocompression process. At this time the metal layer 176 is formed at the interface between the bonding wire 175 and the bonding pad 171.
Finally, the entire structure shown in FIG. 48 is sealed with the molding resin 177 to obtain the structure shown in FIG. 36.
FIG. 49 is a cross-sectional view showing a part of the structure shown in FIG. 34 and further a part of it in an enlarged manner. Usually, a passive film 133, mainly formed of Al2O3 and having a thickness of about 1 to 3 nm, is formed on the surface of the bonding pad 126 (strictly speaking, on the surface of the aluminum alloy film 126b) by the effect of the etching process for forming the opening 129.
FIG. 50 is a cross-sectional view showing a part of the structure shown in FIG. 35 and further a part of it in an enlarged manner. Bonding the bonding wire 130 made of gold to the bonding pad 126 made of an aluminum alloy utilizes the mechanism of destroying the passive film 133 on the surface of the bonding pad 126 by, e.g. ultrasonic waves or thermocompression, and causing gold and aluminum to react at the interface between the bonding wire 130 and the bonding pad 126, so as to form the metal layer 131 which is a layer of a compound of the two elements.
Accordingly, enhancing the bonding strength to obtain a stable connection requires temperature and mechanical pressure enough to destroy the passive film 133 and satisfactorily form the metal layer 131 at the interface. Hence, as the device is downsized and the bonding pad 126 and the bonding wire 130 are reduced in size or diameter, it is necessary to apply higher compression strength or higher ultrasonic strength per unit area.
However, increasing the compression strength or ultrasonic strength may cause the bonding pad 126 to peel off the fourth interlayer insulating film 122 underlying the bonding pad 126, or may make cracks in the fourth interlayer insulating film 122.
FIG. 51 is a cross-sectional view showing a part of the structure shown in FIG. 47 and further a part of it in an enlarged manner. Copper is more susceptible to oxidization than aluminum and the self-passivation effect of the oxide film (CuO) formed on the copper surface is smaller than that of the oxide film formed on the aluminum surface. Therefore, when the top surface of the bonding pad 171 is exposed by the formation of the opening 174, the top surface of the bonding pad 171 is quickly oxidized to form a relatively thick oxide film 178 of about 5 to 10 nm in thickness.
FIG. 52 is a cross-sectional view showing part of the structure shown in FIG. 48 and further a part of it in an enlarged manner. The relatively thick oxide film 178 is formed on the top surface of the bonding pad 171 as shown in FIG. 51. The oxide film 178 cannot be sufficiently destroyed by widespread conventional process such as the ultrasonic or thermocompression wire bonding. Therefore the metal layer 176 cannot be formed uniformly at the interface between the bonding wire 175 and the bonding pad 171, which leads to poor reliability and stability at the connection. This problem will become more serious as the device is further downsized and the bonding pad 171 and the bonding wire 175 are further reduced in size or diameter.
Some methods are suggested to solve this problem: for example, a method in which wire bonding is conducted in a reducing atmosphere with hydrogen gas, or a flip chip method in which metal bumps of gold, solder, etc. are formed on the pad electrodes without wire bonding. However, these methods have other problems such as poor stability, increased cost, etc.
Furthermore, when a redundancy circuit is formed in the semiconductor device shown in FIG. 36, fuses of the redundancy circuit are formed of copper interconnections in the uppermost layer. However, since copper has lower thermal conductivity than aluminum, completely blowing (cutting) the fuses requires higher blowing energy than blowing fuses made of aluminum or an aluminum alloy. Accordingly, in semiconductor devices having multilayer copper interconnection structure, the fuses of redundancy circuits made of copper interconnections may not be properly blown out, leading to reduced yield.
It is an object of the present invention to obtain a semiconductor device having a multilayer interconnection structure using low-resistance copper interconnections, bonding wires can be bonded to bonding pads with enhanced reliability and stability at the connections. It is still an object of the present invention to obtain a semiconductor device in which the performance of blowing the fuses of redundancy circuits can be enhanced in a semiconductor device having a multilayer interconnection structure using copper interconnections.
The semiconductor device includes a multilayer interconnection structure in which a plurality of interconnection layers are formed in an insulating film. The multilayer interconnection structure has a first metal film, a second metal film and a third metal film. The first metal film is made of a first material and functions as a first interconnection belonging to an interconnection layer other than an uppermost interconnection layer. The second metal film is made of a second material and functions as a second interconnection belonging to the uppermost interconnection layer. The second material has a lower resistance and is more susceptible to oxidation than the first material. The third metal film is made of the first material, belongs to an interconnection layer other than the uppermost interconnection layer and functions as a bonding pad. The semiconductor device further includes an opening and a bonding wire. The opening is formed in the insulating film and has its bottom defined by the third metal film. The bonding wire is connected to the third metal film through the opening.
In the semiconductor device according to the present invention, the bonding pad is formed not of the easily-oxidized second material but of the first material less susceptible to oxidation than the second material. Accordingly the bonding wire can be bonded to the bonding pad with enhanced connecting reliability and stability.
According to a second aspect of the present invention, the semiconductor device includes a multilayer interconnection structure in which a plurality of interconnection layers are formed in an insulating film. The multilayer interconnection structure has a first metal film, a second metal film and a third metal film. The first metal film is made of a first material and functions as a first interconnection belonging to an interconnection layer other than an uppermost interconnection layer. The second metal film is made of a second material and functions as a second interconnection belonging to the uppermost interconnection layer. The second material has a lower resistance and a lower thermal conductivity than the first material. The third metal film is made of the first material, belongs to an interconnection layer other than the uppermost interconnection layer and functions as a fuse of a redundancy circuit. The semiconductor device further includes an opening. The opening is formed in the insulating film and has its bottom defined above the third metal film.
The fuse of the redundancy circuit is made not of the second material having a lower thermal conductivity, but of the first material having a higher thermal conductivity than the second material. Accordingly it is possible to obtain stable performance to blow the fuse.
Since the fuse is formed in a lower interconnection layer below the uppermost layer, variations in thickness of the insulating films above and below the fuse can be smaller than when the fuse is formed in the uppermost interconnection layer. As a result the stability of the blowing performance can be further enhanced.